HDLBITS-CS450

timer

timer

模拟一个计时器,当Load为1时,载入data,指定其为倒计时的时间;当load为0时,时间减一.当倒计时结束时将tc输出为高电平

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
    reg[9:0] ct;
    always @(posedge clk)begin
        if (load)begin
            ct <= data;
        end else begin
            if (ct == 0)begin
                ct <= 0;
            end else begin
                ct <= ct - 1;
            end
        end
    end
    assign tc = (ct ==0) ? 1 : 0;
endmodule

counter 2bc

counter 2bc

模拟一个二位计数器,当train_valid为高电平时,计数器根据train_taken改变状态,如果高电平则加一,反之减一.当计数器减少到0时,将不会再减少,而是保持原状;增加到3时,将不会再增加,而是保持原状.areset为异步复位,将计数器复位到2'b01

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    always @(posedge clk or posedge areset)begin
        if (areset)begin
            state <= 2'b01;
        end else begin
            if (train_valid)begin
                if (train_taken)begin
                    state <= state < 3 ? state + 1 : 3;
                end else begin
                    state <= state > 0 ? state-1 : 0;
                end
            end
            else begin
                state <= state;
            end
        end
    end
endmodule

history shift

history shift1

history shift2

32位历史移位寄存器,并搭配回滚功能.

当predict_valid为高电平时,表示当前正处于预测状态,寄存器从LSB一侧移入一位预测的结果(predict_taken)

当mispredicted为高电平时,意味着预测发生错误,此时寄存器必须回滚到发生错误之前的状态(这里原文说的是"冲刷流水线"),并丢弃那些错误发生之后的状态(younger)

当predict_valid,mispredicted同时发生,后者优先级更高

module top_module(
    input clk,
    input areset,

    input predict_valid,
    input predict_taken,
    output reg[31:0] predict_history,

    input train_mispredicted,
    input train_taken,
    input [31:0] train_history
);
    always @(posedge clk or posedge areset)begin
        if (areset)begin
            predict_history = 32'd0;
        end
        else begin
            if (train_mispredicted)begin
                predict_history <= {train_history[30:0],train_taken};
            end
            else if (predict_valid)begin
                predict_history <= {predict_history[30:0],predict_taken};
            end
            else begin
                predict_history <= predict_history;
            end
        end
    end
endmodule

gshare

gshare

根据题意,我们要增加128个2位PHT(pattern history table,模式匹配表),PHT根据7位train_history与7位train_pc异或结果进行寻址

电路分为两大部分:预测+训练.两者分别参考history shift与counter 2bc

module top_module(
    input clk,
    input areset,

    input  predict_valid,
    input  [6:0] predict_pc,
    output predict_taken,
    output reg[6:0] predict_history,

    input train_valid,
    input train_taken,
    input train_mispredicted,
    input [6:0] train_history,
    input [6:0] train_pc
);
    reg[1:0] PHT[127:0];
    integer i;
    always @(posedge clk or posedge areset)begin
        if (areset)begin
            predict_history <= 0;
            for (i = 0; i < 128; i++)begin
              PHT[i] <= 2'b01;
            end
        end
        else begin
            if (train_valid && train_mispredicted)begin
                predict_history <= {train_history[5:0],train_taken};
            end else if (predict_valid) begin
                predict_history <= {predict_history[5:0], predict_taken};
            end
            
            if (train_valid)begin
                if (train_taken)begin
                	PHT[train_history ^ train_pc] <= PHT[train_history ^ train_pc] == 2'b11 ? 
                		2'b11 : PHT[train_history ^ train_pc] + 1;
            	end else begin
                	PHT[train_history ^ train_pc] <= PHT[train_history ^ train_pc] == 2'b0 ? 
                		2'b0 : PHT[train_history ^ train_pc] - 1;
                end
            end
        end
                    
    end
    assign predict_taken = PHT[predict_history ^ predict_pc][1];
    
endmodule